Timekeeping is an important function of computer systems. After boot-up, a system clock of a microprocessor (MPU) is initialized to keep time according to the number of clock cycle updates that it receives. In a first configuration, the MPU uses a counter, a reference value, and an accumulator for keeping track of time in the system clock.
Typically, an MPU has a core-clock distribution network that is part of the system clock. The core-clock distribution network is referred to as the core “mesh-clock”. Every clock cycle, a counter within the mesh-clock increases its count value. If the value of the counter equals a preset reference value, a signal is sent to an accumulator within the mesh-clock. The signal that is sent to the accumulator represents an incremental increase in time. This time is used as MPU system-time, for use with such things as time-stamping files, and so forth. After the signal is sent to the accumulator, the counter is reset to zero, and the counter continues to receive time pulses and send accumulator updates each time the reference value is matched. The reference value is set by the MPU. The reference value is a function of the number of clock cycles of the processor per given unit of time.
However, there is a problem with this approach. It can be desirable for the MPU to change its frequency of operation in the middle of a time count. For instance, the MPU is to change from 1 GHZ to 1.33 GHZ when the count of the counter of the mesh-clock is one or more, but the count does not equal the reference value. This creates a problem. If the MPU keeps the original reference value as the trigger, the timing pulse to the accumulator will originate too quickly and the MPU clock will be too fast. If the MPU changes mid-count to the new reference value, the time increment can be inaccurate for that time period. Furthermore, this error is cumulative. In other words, if the frequency switch occurs a plurality of times, the errors from each switch will add together over time and can be substantial.
In a second approach, the counter of the mesh-core receives its counts directly from a “free-running clock” at a fixed frequency, and not as a function of the frequency of the MPU. The free-running clock can be provided as an external source to the MPU or as a separate internal clock that does not change frequency with the frequency of the MPU. In this implementation, the counter is reset after each addition (or couple of additions). The reset is a function of the MPU clock speed. In this approach, the MPU gives a signal to read the number of oscillations of the free-running clock, and this is added to the accumulator of the core-mesh (the timekeeper that is keeping track of the core frequency count). In this aspect, the counter sends the total count since the last reset to the core clock in parallel and simultaneously with the update signal to the accumulator. The count is added to the accumulator each time the update signal is detected.
An advantage of this approach is that the core mesh-clock can have its own operating frequency (which is slower than the free-running clock), and the ratio between the free-running clock and the mesh-clock can be variable. The accumulator of the core-mesh receives the number representing the previous number of oscillations since the last oscillation in parallel and adds this to its current value.
However, one problem with this free-running clock implementation is that the skew between the free-running clock and the core mesh-clock of the PU must be matched. Skew can generally be defined as the delay between a transition from one logic level to another logic level. Because the accumulator which resides in the core mesh-clock domain is receiving the update signal and count in parallel, all signal transitions must be received by the core clock before it sends a reset signal to the counter. As the parallel signals can have differing transmission speeds, the core mesh-clock cannot be sure when the accumulator has received an accumulated count before sending the reset signal to the counter.
One way to compensate for the skew is to require some kind of feedback between the core clock and the free-running clock to inform the free-running clock the actual signal has been received by the accumulator by the core mesh-clock. But this creates a recursion problem—that is, when does one clock system stop acknowledging the acknowledgment of a second clock system. Furthermore, the free-running clock always has to be the fastest clock, or else the required size of the counter increases in an unbounded fashion. Finally, with parallel propagation of signals, the potential arises for many long wires and signal re-powering circuitry that can be costly to the implementation.
Therefore, there is a need for a method of changing the clock speed of a chip without disrupting the timekeeping ability of the chip in a way that addresses at least some of the problems associated with conventional methods to change clock frequencies on a chip.